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Memory refresh is the process of periodically reading information from an area of computer memory and immediately rewriting the read information to the same area without modification, for the purpose of preserving the information.〔"refresh cycle" in 〕 Memory refresh is a background maintenance process required during the operation of semiconductor dynamic random access memory (DRAM), the most widely used type of computer memory, and in fact is the defining characteristic of this class of memory. In a DRAM chip, each bit of memory data is stored as the presence or absence of an electric charge on a small capacitor on the chip.〔 As time passes, the charges in the memory cells leak away, so without being refreshed the stored data would eventually be lost. To prevent this, external circuitry periodically reads each cell and rewrites it, restoring the charge on the capacitor to its original level. Each memory refresh cycle refreshes a succeeding area of memory cells, thus repeatedly refreshing all the cells in a consecutive cycle. This process is conducted automatically, in the background, by the memory circuitry, while the computer is on, and is transparent to the user.〔 While a refresh cycle is occurring the memory is not available for normal read and write operations, but in modern memory this "overhead" time is not large enough to significantly slow down memory operation. Computer memory that does not require refreshing is available, called static random access memory (SRAM).〔 SRAM circuits take up more room on the semiconductor chip, because each SRAM memory cell requires four to six transistors, compared to a single transistor and a capacitor for DRAM. For this reason, the storage capacity of SRAM chips is much less than DRAM, so SRAM memory is more costly per bit. Therefore, DRAM is used for the main memory in computers, video game consoles, graphics cards and most other large uses of semiconductor memory. The need for extra circuitry to perform memory refresh makes DRAM circuits and their timing significantly more complicated than SRAM circuits, but the great advantages of DRAM in density and cost justify this complexity. == How DRAM refresh works == While the memory is operating, each memory cell must be refreshed repetitively, within the maximum interval between refreshes specified by the manufacturer, which is usually in the millisecond region. Refreshing does not employ the normal memory operations (read and write cycles) used to access data, but specialized cycles called ''refresh cycles'' which are generated by separate counter circuits in the memory circuitry and interspersed between normal memory accesses. The storage cells on a memory chip are laid out in a rectangular array of rows and columns. The read process in DRAM is ''destructive'' and removes the charge on the memory cells in an entire row, so there is a row of specialized latches on the chip called sense amplifiers, one for each column of memory cells, to temporarily hold the data. During a normal read operation, the sense amplifiers after reading and latching the data, rewrite the data in the accessed row〔〔 on ( The Chip Collection, Smithsonian website )〕 before sending the bit from a single column to output. So the normal read electronics on the chip has the ability to refresh an entire row of memory in parallel, significantly speeding up the refresh process. A normal read or write cycle refreshes a row of memory, but normal memory accesses cannot be relied on to hit all the rows within the necessary time, necessitating a separate refresh process. Rather than use the normal read cycle in the refresh process, to save time an abbreviated cycle called a refresh cycle is used. The refresh cycle is similar to the read cycle, but executes faster for two reasons: *For a refresh, only the row address is needed, so a column address doesn't have to be applied to the chip address circuits. *Data read from the cells does not need to be fed into the output buffers or the data bus to send to the CPU. The refresh circuitry must perform a refresh cycle on each of the rows on the chip within the refresh time interval, to make sure that each cell gets refreshed. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Memory refresh」の詳細全文を読む スポンサード リンク
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